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INTEGRATED CIRCUITS
DATA SHEET
SAA7158 Back END IC
Preliminary specification File under Integrated Circuits, IC02 July 1994
Philips Semiconductors
Preliminary specification
Back END IC
FEATURES * Line Flicker Reduction (LFR) by means of MEDIAN filtering * Vertical zoom * Digital colour transient improvement * Digital luminance peaking * Movie phase detection * 4:4:4 YUV data throughput selectable, standard is 4:1:1 Y/U/V * D/A conversion * UART interface. GENERAL DESCRIPTION Application Environment
SAA7158
The Back END IC (abbreviated as BENDIC) is designed to cooperate with an 8051 type of microprocessor, the ECO3 (SAA4951) memory controller and Texas Instruments TMS4C2970 memories, but other configurations may be applicable. Fig.1 shows the block diagram of the feature box. The nominal clock frequency of the IC is 27 MHz or 32 MHz, with a maximum of 36 MHz. The system supports the digital Y/U/V bus for selection of different video signal sources. The Y/U/V bus and the BENDIC data input are fully synchronous with respect to the clock signal. A line reference signal BLN for timing control purposes has to be provided by external elements which always controls the system timing, independent of active signal sources or desired functions. Analog Characteristics The BENDIC contains 3 independent, high speed digital to analog converters for luminance and colour difference signal processing and conversion. The resolution of the two DA converters for the colour difference signals is 8 bit. The luminance peaking up to 6 dB at high frequencies widens the resolution of the luminance channel. To avoid aliasing effects due to time discrete amplitude limiting the resolution of 9-bit is offered for the luminance conversion. All output stages provide high performance output stages for driving lines with low impedance line termination. QUICK REFERENCE DATA SYMBOL VDD Tamb digital supply voltage analog supply voltage operating ambient temperature PARAMETER MIN. 4.5 4.75 0 MAX. 5.5 5.25 +70 UNIT V V C
ORDERING INFORMATION EXTENDED TYPE NUMBER SAA7158WP Note 1. SOT188-2; 1996 November 26. PACKAGE PINS 68 PIN POSITION PLCC MATERIAL plastic CODE SOT188(1)
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Philips Semiconductors
Preliminary specification
Back END IC
SAA7158
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Fig.1 Block diagram of the feature box.
Philips Semiconductors
Preliminary specification
Back END IC
PINNING SYMBOL TEST1/AP Y0-0 Y0-1 Y0-2 Y0-3 Y0-4 Y0-5 VDD1 VSS1 Y0-6 Y0-7 UV0-0 UV0-1 UV0-2 UV0-3 TEST2/SP RE2_OUT RE1_OUT RSTR RE2_IN RE1_IN BLN PCL PDA VSS2 CLK VDD2 V1-0/Y2-0 V1-1/Y2-1 V1-2/Y2-2 V1-3/Y2-3 V1-4/Y2-4 V1-5/Y2-5 V1-6/Y2-6 V1-7/Y2-7 U1-0/UV2-0 U1-1/UV2-1 U1-2/UV2-2 U1-3/UV2-3 VSS3 July 1994 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 input 3-state output 3-state output 3-state output 3-state output 3-state output 3-state output supply ground 3-state output 3-state output 3-state output 3-state output 3-state output 3-state output input output output input input input input input in/output ground input supply input input input input input input input input input input input input ground TYPE DESCRIPTION action pin for testing; to be connected to VSS feedback_data to second memory, Y bit 0 feedback_data to second memory, Y bit 1 feedback_data to second memory, Y bit 2 feedback_data to second memory, Y bit 3 feedback_data to second memory, Y bit 4 feedback_data to second memory, Y bit 5 positive digital supply voltage (+5 V) digital ground feedback_data to second memory, Y bit 6 feedback_data to second memory, Y bit 7 feedback_data to second memory, UV bit 0 feedback_data to second memory, UV bit 1 feedback_data to second memory, UV bit 2 feedback_data to second memory, UV bit 3 shift pin for testing; to be connected to VSS redirected read enable to memory 2 redirected read enable to memory 1
SAA7158
memory read, P interface and movie detection reset input for read enable to memory 2 input for read enable to memory 1 blanking signal clock for interface with 8051 UART, mode 0 data for interface with 8051 UART, mode 0 digital ground master clock, nominal 27 (32) MHz positive digital supply voltage (+5 V) V data, bit 0 in 4:4:4; Y data second memory, bit 0 V data, bit 1 in 4:4:4; Y data second memory, bit 1 V data, bit 2 in 4:4:4; Y data second memory, bit 2 V data, bit 3 in 4:4:4; Y data second memory, bit 3 V data, bit 4 in 4:4:4; Y data second memory, bit 4 V data, bit 5 in 4:4:4; Y data second memory, bit 5 V data, bit 6 in 4:4:4; Y data second memory, bit 6 V data, bit 7 in 4:4:4; Y data second memory, bit 7 U data, bit 0 in 4:4:4; UV data second memory, bit 0 U data, bit 1 in 4:4:4; UV data second memory, bit 1 U data, bit 2 in 4:4:4; UV data second memory, bit 2 U data, bit 3 in 4:4:4; UV data second memory, bit 3 digital ground 4
Philips Semiconductors
Preliminary specification
Back END IC
SAA7158
SYMBOL U1-4/UV1-0 U1-5/UV1-1 U1-6/UV1-2 U1-7/UV1-3 Y1-0 Y1-1 Y1-2 Y1-3 Y1-4 Y1-5 Y1-6 Y1-7 VSUB RFHY RFLY RFLC RFHC VDDA4 CUR VDDA3 AY VSSA3 VDDA2 AU VSSA2 VSSA1 AV VDDA1
PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 input input input input input input input input input input input input
TYPE
DESCRIPTION U data, bit 4 in 4:4:4; UV data first memory, bit 0 U data, bit 5 in 4:4:4; UV data first memory, bit 1 U data, bit 6 in 4:4:4; UV data first memory, bit 2 U data, bit 7 in 4:4:4; UV data first memory, bit 3 Y data first memory, bit 0 Y data first memory, bit 1 Y data first memory, bit 2 Y data first memory, bit 3 Y data first memory, bit 4 Y data first memory, bit 5 Y data first memory, bit 6 Y data first memory, bit 7 substrate pin; connect to analog ground (VSSA) connect C = 100 nF to analog ground (VSSA) connect to analog ground (VSSA) connect to analog ground (VSSA) connect C = 100 nF to analog ground (VSSA) analog supply voltage for reference ladders of the three DA converters and for current sources of the output buffers current input for analog output buffers (0.4 mA from VDDA4 = 5 V); connect with R = 15 k analog supply voltage for output buffer AY analog luminance Y output analog ground for output buffer AY analog supply voltage for output buffer AU analog (B-Y) or -(B-Y) output analog ground for output buffer AU analog ground for output buffer AV analog (R-Y) or -(R-Y) output analog supply voltage for output buffer AV
analog ground analog input analog input analog input analog input analog supply analog input analog supply analog output analog ground analog supply analog output analog ground analog ground analog output supply
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Philips Semiconductors
Preliminary specification
Back END IC
SAA7158
Fig.2 Pin configuration.
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Philips Semiconductors
Preliminary specification
Back END IC
FUNCTIONAL DESCRIPTION Block Diagram
SAA7158
The BENDIC will be produced in a CMOS double metal process. It is possible to feed the BENDIC with 8-bit wide luminance and chrominance signals Y/U/V in 4:1:1 mode from the digital Y/U/V bus and to run it in a bypass mode with Y/U/V in 4:4:4 mode without any bandwidth reduction. The BENDIC contains the processing functions as depicted in Fig.3. Following functions are available: Datapath: * 1H - 4:1:1 line memory, 852 words by 8-bits luminance + 4-bits multiplexed chrominance * REFORMATTER to get 8-bit wide UV from the Y/U/V bus format * MIX UV and MIX Y to interpolate between actual and 1H-delayed input signals, programmable for realization of vertical zoom * MEDIAN filter in luminance processing path for line flicker reduction * MOVIE PHASE DETECT for supporting line flicker reduction control * PEAKING for luminance channel * UPSAMPLING and DCTI for chrominance transient improvement * HOLD/GREY/BLANK blocks for blanking and grey level insertion * RE PROCESSING controls read enable for first and second memory, outputs are programmable for different applications * Data switches for field select, mix/median select, 4:1:1/4:4:4 select * DAC blocks for digital to analog conversion of Y, U, V video signals * REGISTER with 3-state control for direct output of Y/U/V 1 input to memories. Control: * P INTERFACE for the control of BENDIC functions, including zoom control * TIMING CONTROL and TEST as support blocks. All video data signal processing inside the BENDIC is phaselinear and nonrecursive (except line delay in recirculation mode).
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Preliminary specification
Back END IC
SAA7158
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Fig.3 Block diagram.
Philips Semiconductors
Preliminary specification
Back END IC
Data Path Signal processing * 1H - 4:1:1 line memory, 852 words by 8-bits luminance + 4-bits multiplexed chrominance The Y/U/V line memory is organized as 852 x 12 bits. It works as a shift register with recirculation mode if desired. The line start is synchronized to RE, and if there are more than 852 words to be stored it will stop and hold. * REFORMATTER to get 8-bit wide UV from the Y/U/V bus format The reformatter changes the 4:1:1 format of UV signals into a sequential 8-bit U and V data stream with a sampling rate of half the master clock. * MIX UV and MIX Y to interpolate between actual and 1H-delayed input signals, programmable for realization of vertical zoom The function of the MIX-blocks is to interpolate between two input sources A and B (original signal and 1H-delayed signal). Possible interpolation coefficients 3 1 1 are { 1 or -- or ---- or ---- or 0 } x ( A - B ) + B. 4 2 4 * MEDIAN filter in luminance processing path for line flicker reduction The median filter consists of two different median filters working in parallel with full clock rate. Filters for up and downsampling are implemented with an 8-bit output. * MOVIE PHASE DETECT for supporting line flicker reduction control A pixel by pixel luminance level comparison is made on the active video of two consecutive fields from the memory. The absolute difference of the 4 most significant bits of each pixel from the two fields is added to the accumulated value of the current field in a register. The highest significant two bytes thereof are transferred during field blanking period with rising edge of RSTR signal into a register that can be read via the P interface. After reading the register will be cleared. * PEAKING for luminance channel The H-peaking of the luminance channel compensates the bandwidth reduction caused by various components of the TV signal processing chain. Because of the possibility to convert over and undershoots it is even possible to precompensate the si-amplitude attenuation of the D/A converter by 6 dB. The absolutely phaselinear filters can be programmed: frequency response, amplitude of the high frequency signals and degree of coring is controlled via the P interface. Frequency responses c. f. separate application sheet. July 1994 9
SAA7158
* UPSAMPLING and DCTI for chrominance transient improvement After upsampling of U and V, in the DCTI block the U and V signals are processed with a look-backwards/look-forwards device. The chrominance signal values are stored in a 26 tap pixel delay line. Controlled by a multiplexer select signal K the values are read from the pixel delay line into the output registers of DCTI. The calculation of the K signal is done within this block. To determine the number of steps to look back and dV d dU forwards the following relation is used: ---- ------- + ------- . dt dt dt U and V are processed serially with the same circuitry. The final upsampling towards the master clock for D/A conversion is part of the algorithm and done by linear interpolation between two adjacent taps of choice. It is controlled by the K signal too. * HOLD/GREY/BLANK blocks for blanking and grey level insertion The function of these blocks is to insert desired levels for Y, U and V, where no active video is present. BLANKing is performed during line and field blanking period indicated by BLN. GREY is performed where RE indicates that the memory is not read out, and pixel repetition is switched off by the P interface; the grey value comes via the P interface. HOLD is performed if pixel repetition is selected by the P interface; the last value of Y, U and V is kept until RE is active again. * RE PROCESSING controls read enable for first and second memory Here the output signals RE1 and RE2 are shifted by adding a programmable delay of 5, 6, 7 or 8 clock pulses with respect to the input signals. In addition RE1 will be influenced in case of zoom. * data switches for field select, mix/median select, 4:1:1/4:4:4 select The switches shown in the block diagram Fig.3 are controlled via the P interface and allow control of the data streams inside the BENDIC. * DAC blocks for digital to analog conversion of Y, U, V video signals The D/A conversion is performed in the DAC blocks. The converters consist of the resistor strings to be connected externally and three buffers with a 25 serial resistor at the output built in. To get 75 impedance externally three 50 resistors have to be used near the pins. The capacitive load at the outputs should not exceed 30 pF.
Philips Semiconductors
Preliminary specification
Back END IC
* REGISTER with 3-state control for direct output of Y/U/V 1 input to memories The 3-state switch with internal register is supplied for the feedback data to the second memory. The feedback bus is a copy of the field 1 bus, but with 4 clockpulses delay. 3-state control is done via P interface. The control signals CLK Line locked clock of maximal 36 MHz. This is the system clock. Within the BENDIC the CLK signal is distributed to the different blocks. BLN Blanking NOT signal. This signal marks the horizontal and vertical blanking and defines with its rising edge the start phase of the UV 4:1:1 format. A programmable delay of 0, 1, 2 or 3 clock pulses shifts the internal pulse with respect to the input. RE1_in Read enable memory 1 signal. This signal is generated by the memory controller and its HIGH state determines the read enable on the first memory bank, after it is processed by BENDIC for the ZOOM mode and fine shift of the edges. RE2_in Read enable memory 2 signal. This signal is generated by the memory controller and its HIGH state determines the read enable on the second memory bank, including a fine shift of the edges. note: RE1_in and RE2_in are processed in the BENDIC to: * external signals: RE1_out and RE2_out * RE with correct internal delay to match datapath delays, is used to define the edges between video and side panels (grey insertion or pixel repetition). RSTR Reset signal This signal is transferred (asynchronous with CLK) by e. g. a microprocessor to reset the communication between the microprocessor and the BENDIC. CLK has to be present in this case. In a typical application, RSTR is an active HIGH pulse, issued only in the vertical blanking period. During RSTR HIGH-state, the `feedback_data' lines are switched to 3-state, temporarily overruling the mode that has been set by the microprocessor. By this provision, RSTR can be used to prevent data collision on the 3-state databus, e. g. during a power on sequence. Also, this signal is used to transfer the `movie phase detect' data to a register that can be read by the microprocessor. July 1994 10
SAA7158
PCL Microprocessor interface clock signal This signal is transferred (asynchronous with CLK) by a microprocessor (8051, UART mode 0) as communication clock signal at 1 MHz. PDA Microprocessor interface data signal This signal is transferred or received (asynchronous with CLK) by a microprocessor (8051, UART mode 0) as communication data signal at 1 MBaud, related to PCL. Data is valid the rising edge of PCL. The external control The P interface has the following functions: * Receive settings from the P * Transmit movie phase detect data to the P The interface is based on a two wire interface, one for clock, the other for bidirectional data form. It is compatible with the 8051 family UART mode 0 interface. The P is the master of the communication, it generates the clock (nominal 12 MHz/12 = 1 MHz), only active when transfer is done. The protocol for the communication is: 8 addressbits are sent by the P (LSB first), if the address is a write address then 8 databits (LSB first) are sent by the P, else (if the address is a read address) 8 databits are sent by BENDIC. RSTR is used to reset the phase of the address/data transfer. The negative going edge of RSTR clears the address register. After reset the first transmitted bit is to be taken as the first (LSB) bit of an address. For field1/field2 selection and for mix/median selection, 4 addresses are used to select each of the four combinations. A databyte is not obligatory after each of these four addresses, but a dummy databyte is needed if the transmission is to be followed by a further one.
Philips Semiconductors
Preliminary specification
Back END IC
Table 1 Write address table. FUNCTION dataformat setting bit2: invUV bit3: UV8bit bit4: UVbin bit5: Yclip bit6: 4:4:4 bit7: feedback 2 grey value setting bit4: grey(0) bit5: grey(1) bit6: grey(2) bit7: grey(3) 3 read enable setting bit0: re1_d(0) bit1: re1_d(1) bit2: inv_re1 bit3: re2_d(0) bit4: re2_d(1) bit5: inv_re2 bit6: bln_d(0) bit 7: bln_d(1) 4 zoom setting bit0: lps bit1: pixrep bit2: black16 bit3: zoom(0) bit4: zoom(1) bit5: zoom(2) bit6: zoom(3) bit7: zoom(4) 5 CTI setting bit4: range(0) bit5: range(1) bit6: gain(0) bit7: gain(1) 6 peaking setting, average UV select bit0: av_w_med bit1: WG(0) bit2: WG(1) bit3: BFB bit4: BP(0) bit5: BP(1) bit6: coring(0) bit7: coring(1) BIT
SAA7158
ADDRESS (HEX) 1
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Preliminary specification
Back END IC
SAA7158
ADDRESS (HEX) 7C 7D 7E 7F
FUNCTION multiplexer setting multiplexer setting multiplexer setting multiplexer setting
BIT SET select field1 OFF; select median OFF (all databits are dummy) SET select field1 ON; select median OFF (all databits are dummy) SET select field1 OFF; select median ON (all databits are dummy) SET select field1 ON; select median ON (all databits are dummy)
The function of the bits in the control datawords are explained below: feedback 4:4:4 Yclip UVbin UV8bit invUV grey(3:0) bln_d(1:0) re2_d(1:0) re1_d(1:0) inv_re2 inv_re1 zoom(4:0) black16 pixrep Ips range(1:0) gain(1:0) coring(1:0) av_w_med BP(1:0) WG(1:0) BFB HI: feedback output is 3-state enabled = outputs active HI: YUV-4:4:4 mode selected instead of 4:1:1 mode HI: Y signal after peaking is clipped and converted to 9-bit range HI: UV signals are taken from input as binary signals instead 2's complement HI: UV signals are taken from input as 8-bit values instead of 7-bit HI: UV signals are inverted before the DACs (outputs = -U and -V) determines highest 4 bits in shade of grey in side panels shifts the internal BLN signal from 0 to 3 clock pulses with respect to input shifts 5 to 8 clock pulses the RE2 output signal versus input shifts 5 to 8 clock pulses the RE1 output signal versus input, additionally influenced by zoom HI: RE2 output is polarity reversed in relation to RE2 input HI: RE1 output is polarity reversed in relation to RE1 input determines vertical zoom factor, which is (32/zoom(4:0)); zoom(4:0) = 0 is equivalent to no zoom HI: the Y signal value during the blanking period is 16 instead of 0 HI: side panels have the same Y, U and V as on the edge of the last video information HI: functional test mode for line on line median on/off determines maximum in CTI range of looking back/looking forward determines gain of CTI function determines coring level in Y peaking enable average UV while median in Y (UV := 1/2 x direct + 1/2 x delayed) determines frequency response in Y peaking determines weighted addition in Y peaking with 1 or 1/2 or 1/4 or 0 HI: determines bypass for BF1 in Y peaking
The BENDIC provides the correlation of two subsequent fields with its `Movie phase detector' via the P interface. The MSB or LSB values of this correlation factor is read from the BENDIC by sending an addressbyte and subsequently receiving a databyte from it, according to Table 2.
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Philips Semiconductors
Preliminary specification
Back END IC
Table 2 Read address table. BIT bit0: corr(0) bit1: corr(1) bit2: corr(2) bit3: corr(3) bit4: corr(4) bit5: corr(5) bit6: corr(6) bit7: corr(7) ADDRESS (HEX) 81 bit0: corr(8) bit1: corr(9) bit2: corr(10) bit3: corr(11) bit4: corr(12) bit5: corr(13) bit6: corr(14) bit7: corr(15) BIT
SAA7158
ADDRESS (HEX) 80
corr(15:0) is the measured Y correlation factor between two successive fields.
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Preliminary specification
Back END IC
CHARACTERISTICS Specification of input/output and clock levels and timing The following table shows the specifications of input/output/clock levels and timing for Tamb = 0 to +70 C; VDD = 4.5 to 5.5 V; VDDA = 4.75 to 5.25 V unless otherwise specified. SYMBOL Supply VDD1-2 VDDA1-4 IDD1-2 IDDA1-4 VIL VIH ILI CIC CID CIZ ICUR VOH VOL Timing tCLK kCLK tr tf tSU tHD tOH tOD Cld RSLY RSLC B CT CLK cycle time CLK duty cycle tCLK-HIGH/tCLK CLK rise time CLK fall time input data setup time input data hold time output data hold time output data delay time note 2 note 2 27 40 - - - - 6 - - - - - - - - - - 41 60 5 6 5 6 - 25 digital supply voltages analog supply voltages supply current digital supply current analog note 1 4.5 4.75 - - -0.5 2.0 - - - - - - - - - - - - - - - - - - 5.5 PARAMETER CONDITIONS MIN. TYP.
SAA7158
MAX.
UNIT
V V mA mA
5.25 250 18 +0.8 VDD + 0.5 10 10 10 10
Digital inputs LOW level input voltage HIGH level input voltage input leakage current input capacitance (clocks) input capacitance (data) input capacitance (I/O in high Z) V V A pF pF pF
Reference and current inputs input current 0.4 mA
Digital outputs HIGH level output voltage LOW level output voltage note 2 note 2 2.4 0 VDD1-2 0.6 V V
ns % ns ns ns ns ns ns
Data output loads (3-state outputs) output load capacitance 10 - - 20 - 35 - - - -42 pF
Characteristics of the DA converters resolution of the Y DAC resolution of the U and V DAC analog signal bandwidth (-3 dB) crosstalk between channels 9 8 - - bit bit MHz dB
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Preliminary specification
Back END IC
SAA7158
SYMBOL DNL INL Vout Notes
PARAMETER differential nonlinearity integral nonlinearity output voltage (without load)
CONDITIONS referred to 8 MSB's referred to 8 MSB's - - -
MIN. - -
TYP.
MAX. 0.5 1 -
UNIT LSB LSB V
2 Vp-p
1. fCLK = 36 MHz, fdata = 18 MHz (rectangular full scale); without output load. 2. Timings and levels have to be measured with load circuits 1.2 k connected to 3.0 V (TTL load), and CL = 25 pF. APPLICATION NOTE FOR THE ANALOG PART OF BENDIC The digital to analog conversion is done in parallel for the three channels. The DA converters (8-bit for U and V; 9-bit for Y) are based on resistor strings with low impedance output buffers. They are designed for 2 Vp-p unloaded output swing. To avoid integral nonlinearity errors, the minimum output voltage is 200 mV; so the DC range for unloaded output is between 0.2 and 2.2 V. A serial resistor of 25 is integrated at the outputs of the buffers. With 50 in series - close to the output pins - the nominal output voltage for 75 line termination is 1 Vp-p with a DC range of 0.1 to 1.1 V. Amplitude matching to external requirements has to be done with external dividers. Capacitance load should not exceed 30 pF. The DAC's require three separate analog supply voltages VDDA1-3 and analog ground lines VSSA1-3 for the output buffers. The accuracy of an external voltage reference input VDDA4 directly influences the output amplitude of the video signals. The current input CUR supplies the output buffers with a current of about 0.3 mA at VDDA = 5 V, if a resistor of 15 k is connected to this pin. A larger current improves the output bandwidth but makes the integral nonlinearity worse.
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Preliminary specification
Back END IC
SAA7158
Fig.4 Timing diagram.
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PACKAGE OUTLINE PLCC68: plastic leaded chip carrier; 68 leads
SAA7158
SOT188-2
eD y 60 61 X 44 43 Z E A
eE
bp b1 wM
68
1
pin 1 index e
E
HE A A4 A1 (A 3)
k
9
27
k1
Lp detail X
10 e D HD
26 ZD B
vM A
vMB 0 5 scale 10 mm
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT
mm
A
4.57 4.19
A1 min.
0.51
A3
0.25
A4 max.
3.30
bp
0.53 0.33
b1
0.81 0.66
D (1)
E (1)
e
eD
eE
HD
HE
k
k1 max.
0.51
Lp
1.44 1.02
v
0.18
w
0.18
y
0.10
Z D(1) Z E (1) max. max.
2.16 2.16
24.33 24.33 23.62 23.62 25.27 25.27 1.22 1.27 24.13 24.13 22.61 22.61 25.02 25.02 1.07
45 o
0.180 inches 0.020 0.01 0.165
0.930 0.930 0.995 0.995 0.048 0.057 0.021 0.032 0.958 0.958 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.13 0.890 0.890 0.985 0.985 0.042 0.040 0.013 0.026 0.950 0.950
Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE VERSION SOT188-2 REFERENCES IEC 112E10 JEDEC MO-047AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-03-11
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Preliminary specification
Back END IC
SOLDERING Plastic leaded chip carriers BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is recommended using two solder waves (dual-wave) in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be
SAA7158
applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages). For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
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